VIORFCLKEN=DISABLED, EXTOSCEN=DISABLED, EXTESEL=BOTH_EDGES, APBDIV=DIV1, AHBDIV=DIV1, AHBSEL=LPOSC0, OBUSYF=NOT_SET
Module Control
| AHBSEL | AHB Clock Source Select. 0 (LPOSC0): AHB clock source is the Low-Power Oscillator. 1 (LFOSC0): AHB clock source is the Low-Frequency Oscillator. 2 (RTC0TCLK): AHB clock source is the RTC0TCLK signal. 3 (EXTOSC0): AHB clock source is the External Oscillator. 4 (VIORFCLK): AHB clock source is the VIORFCLK input pin. 5 (PLL0OSC): AHB clock source is the PLL. 6 (LPOSC0_DIV): AHB clock source is a divided version of the Low-Power Oscillator. |
| AHBDIV | AHB Clock Divider. 0 (DIV1): AHB clock divided by 1. 1 (DIV2): AHB clock divided by 2. 2 (DIV4): AHB clock divided by 4. 3 (DIV8): AHB clock divided by 8. 4 (DIV16): AHB clock divided by 16. 5 (DIV32): AHB clock divided by 32. 6 (DIV64): AHB clock divided by 64. 7 (DIV128): AHB clock divided by 128. |
| APBDIV | APB Clock Divider. 0 (DIV1): APB clock is the same as the AHB clock (divided by 1). 1 (DIV2): APB clock is the AHB clock divided by 2. |
| EXTESEL | External Clock Edge Select. 0 (BOTH_EDGES): External clock generated by both rising and falling edges of the external oscillator. 1 (RISING_ONLY): External clock generated by only rising edges of the external oscillator. |
| OBUSYF | Oscillators Busy Flag. 0 (NOT_SET): AHB and APB oscillators are not busy. 1 (SET): AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields should not be modified. |
| VIORFCLKEN | VIORF Clock Enable. 0 (DISABLED): Disable the VIORFCLK input. 1 (ENABLED): Enable the VIORFCLK input. |
| EXTOSCEN | External Clock Input Enable. 0 (DISABLED): Disable the EXTOSC input. 1 (ENABLED): Enable the EXTOSC input. |